In pulse width modulation (PWM) regulators, the control circuit switches a power stage to keep an electrical variable (typically the output voltage) equal to a reference value Vref independently from the current that the regulator delivers to a load connected thereto. Synchronizing switching cycles of two or more PWM regulators with a reference clock is particularly useful because it may allow the regulators to be connected together to share the input filter capacitor, as shown, for example, in FIG. 1. If the turning on of the two high side switches HS1 and HS2 is outphased by about half a period, and the two switches are never simultaneously on (the duty-cycle being smaller than 0.5), the capacitance for the input capacitor is smaller than the sum of the capacitances that each regulator would singularly require. This is a significant advantage in terms of reduction of fabrication costs of regulators. Synchronization is also useful for controlling multiphase converters, wherein an outphasing of 360°/N among the N-phase converters is generally required.
In general, in a voltage regulator including of a plurality of switching converters, synchronizing, in frequency, two or more voltage regulators prevents beat phenomena, and generated switching noise in a component regulator from disturbing the other component regulators simply by properly outphasing them.
A traditionally used technique for synchronizing a regulator includes a reference clock for the turning on the high side switch HS in starting a charge phase. The turn off instant of the HS switch, that starts the discharge phase, is determined by the occurrence of a certain condition on the state variable of the regulator. This topology is indicated in literature as synchronous “clocked Ton” control. The clocked Ton control mode is sensitive to switching noise in case of a relatively short charge time Ton, because the comparator that determines the turn off of the HS switch is influenced by noise generated by the precedent turn on of the HS switch, typically including a sinusoidal disturbance that is dampened by parasitic inductances of the regulator.
By contrast, the technique based on turning off the HS switch synchronously with clock pulses and on turning it on when the output voltage attains a reference value is more robust, even when the charge time Ton is relatively short. It is generally a normal practice to add a compensation ramp to the output voltage signal that is sent to the comparator for ensuring stability (with duty-cycle smaller than 0.5). Unfortunately, the slope of this compensation ramp may be determined taking in consideration the slope of the ripple on the output voltage due to the parasitic resistance ESR of the output capacitor that may be one among a relatively large spread of values.
Other topologies are known in literature. For example, the regulator may comprise a comparator for starting a charge interval (HS on) when the output voltage attains a reference value. This mode of control, commonly referred to as “constant Ton control,” may be implemented, for example, with a regulator as the one shown in FIG. 2. When the output voltage Vout falls below a threshold Ilim or, in general, when a certain condition of state variables of the regulator is attained, the block CONTROL LOGIC commands switching from the discharge state to the charge state through the signals HG and LG and raises the START signal indicating that a charge phase is in progress. The monostable circuit ON TIME DELAY receives the START signal and, after a fixed time Ton, sends the signal OUT to the control logic. The START signal is thus disabled and the regulator starts a discharge phase.
Typically, a minimum duration Toff_min of the discharge phase is set to prevent the regulator from oscillating too fast in transient conditions. With this type of control, the converter is self-oscillating because the working frequency is not tied to a clock, but depends on parameters of the system and on whether it is in steady state or transient condition. The switching PW cycles could hardly be synchronous with an external clock.
The constant Ton control mode is adapted to work with small Ton values because between each turn on (determined by the comparator) of the HS switch and the precedent turn off, there is an interval that is surely longer than (or at most equal to) Toff_min, during which the noise generated at turn off vanishes. The stability of this control is relatively robust to the spread of the equivalent series resistance (ESR) value of the output filter capacitance.
In the same manner, it may be possible to force the turning off of the high side HS switch (starting a discharge phase) when pulses of the clock signal are received and compare the output voltage with the reference for determining the turn on instant of the charge phase (turning on of the high side HS switch). This topology is indicated in literature as “clocked Toff” synchronous control mode.
The output voltage comparator may be used for determining the starting instant of a discharge phase, that again may have a pre-established duration. In this case, this control is referred to as “constant Toff” control mode. The ensuing discussion of inherent shortcomings and problems will refer to the constant “Ton control,” though the same observations hold, for the alternative case, in which the comparator of the output voltage determines the beginning of a discharge phase.
FIG. 3 illustrates a schematic diagram of a circuit used in a traditional constant Ton converter for determining the internal Ton. According to a commonly used technique of PWM driving, the reference voltage Vref and a voltage ramp VC having a slope proportional to the input voltage Vin, are sent to a comparator that generates the signal OUT to terminate a charge phase and to start a discharge phase. The ramp is typically obtained by charging a capacitance C with a current Vin/R proportional to the voltage to be converted Vin input to the converter. With this technique, the PWM frequency may be practically independent from the input voltage.
The limits and drawbacks of this technique may be known in that the functioning is negatively influenced by nonlinearities. In particular, delays of the comparator and of the driver may cause important errors for relatively small values of the charge time Ton. Additionally, for the same charge time Ton, the switching frequency may depend on the load current, because of the resistive drops in the power switches and in the inductor of the regulator.
With τ being the comparator delay between the voltage VC and the reference Vref, D the duty cycle Vout/Vin, Rs the combined series resistance of the power MOS and of the inductor of the regulator, and considering Vref=Vout, the PWM switching period Tsw will be substantially:
      T    SW    ≅            (                        R          ·          C                +                  τ          D                    )        ·          (              1        -                              Rs            ·            Iload                    Vout                    )      
The switching frequency may be affected by a non-negligible spread depending both on internal parameters (τ), as well as external parameters (Rs, Iload, D), thus the circuit of FIG. 2 may be inappropriate in those applications for which such a large spread may be excessive. In particular, for relatively small duty cycles and large values of the target switching frequency 1/(R·C), the parameter τ/D becomes comparable to the product R·C and the resulting error may be as large as about 100%.